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Cake day: June 29th, 2023

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  • beatle@aussie.zonetoComic Strips@lemmy.worldIt's nothing
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    4 months ago

    “I’ll tell you how I feel about school, Jerry: It’s a waste of time. Bunch of people runnin’ around bumpin’ into each other, got a guy up front says, ‘Two plus two,’ and the people in the back say, ‘Four.’ Then the bell rings and they give you a carton of milk and a piece of paper that says you can go take a dump or somethin’. I mean, it’s not a place for smart people, Jerry. I know that’s not a popular opinion, but that’s my two cents on the issue.” — Rick
















  • nanometer is a marketing term now and doesn’t reflect actual sizes. Samsung were first with “3nm”.

    America was doing “3nm” in 2018. You don’t seem to have any understanding of this issue.

    From Wikipedia:

    The term “3 nanometer” has no direct relation to any actual physical feature (such as gate length, metal pitch or gate pitch) of the transistors. According to the projections contained in the 2021 update of the International Roadmap for Devices and Systems published by IEEE Standards Association Industry Connection, a 3 nm node is expected to have a contacted gate pitch of 48 nanometers and a tightest metal pitch of 24 nanometers.

    Also from Wikipedia:

    South Korean chipmaker Samsung started shipping its 3 nm gate all around (GAA) process, named 3GAA, in mid-2022. On 29 December 2022, Taiwanese chip manufacturer TSMC announced that volume production using its 3 nm semiconductor node termed N3 is under way with good yields.

    In early 2018, IMEC (Interuniversity Microelectronics Centre) and Cadence stated they had taped out 3 nm test chips, using extreme ultraviolet lithography (EUV) and 193 nm immersion lithography.